Battery management systems are growing increasingly smarter with innovations in software and hardware that enable more ...
Chipmakers are starting to use AI to manage data that is mined from different “dashboards,” many of which are already ...
For SoC designs that include high-speed, voluminous I/O, it is essential that the prototype be exercised with large amounts ...
This white paper explains how Synopsys Security IP embeds hardware‑rooted protection into AI SoCs and chiplets to secure ...
Synopsys’ Prith Banerjee identifies key challenges in designing AI data centers and why addressing them requires a transformative approach that impacts every aspect of the system design and its ...
Researchers from MIT and the MIT-IBM Watson AI Lab developed a prediction tool that can quickly tell data center operators ...
Semiconductor engineering teams have long relied on an iterative simulation workflow: define the scenario, prepare the model, ...
A new technical paper, “Nonvolatile photonic field-programmable coupler array,” was published by researchers at University of ...
If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common ...
Traditional simulations lack an understanding of clocking requirements and cannot handle the complete clock network of a ...
The boundaries between IP reuse, interconnect design, and hardware-software integration are no longer independent.
Analyze the effects on eye diagrams, BER, and timing margins by integrating advanced equalization algorithms into channel ...
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