EDN

How to Read Data Sheets: Logic Timing (Part 2, Latches)

Who would have thought that a circuit comprising only two 2-input NAND gates could be so complicated (or, should we say, “interesting”)? Up to this point (click here to see my earlier columns), the ...
EDN

How to Read Data Sheets: Logic Timing (Part 3, Flip-Flops)

The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K = Reset) by interpreting the J = K = 1 condition as a “flip” or toggle command. In my previous column, we introduced latches and ...
Semiconductor Engineering

8-In-1 Reconfigurable Logic Gate (TU Dresden)

A technical paper titled “The RGATE: an 8-in-1 Polymorphic Logic Gate Built from Reconfigurable Field Effect Transistors” was published by researchers at TU Dresden and NaMLab. “We present the ...
Hackaday

Patching Together Logic Gates

The digital world offers many advantages over its analog relatives, the use of boolean logic among them. Some of the functions, like NOT, OR, and AND are fairly straightforward and line up nicely with ...