IEEE

Design and Performance Evaluation of an Adaptive Routing Algorithm for RISC-V Based NoC Architecture

Abstract: Due to the increasing complexity of modern System-on-Chip (SoC) designs, classical and multi-layer bus architectures are inadequate for meeting the needs of inter-core communication.
Semiconductor Engineering

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)

A new technical paper titled “Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions” was ...
IEEE

WAFER: Wearable, Ambient-Aware Adversarial Fall Event Detection System Using a RISC-V SoC Architecture

Abstract: Individuals suffering from neurodegenerative diseases, neurological disorders, or going through pregnancy together make up an extensive group of individuals who are affected by adversarial ...