Electronic Design

Development Environment Supports Mixed C++ And HDL Test Benches

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verification capabilities, ...
Design-Reuse

Automatic C-to-VHDL testbench generation shortens FPGA development time

Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad ...
EDN

Revised BestBench tool supports Verilog, VHDL

SAN MATEO, Calif. — Testbench tool provider Diagonal Systems AG (Zurich, Switzerland) has introduced BestBench 4.0, a new version of its HDL design and analysis tool that now includes support for ...
Electronic Design

The MathWorks App Generates HDL Code From System Models

The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces ...
Design-Reuse

DapTechnology announces VHDL Testbench for its FireLink Extended 1394b link layer controller IP Core

Nijmegen, The Netherlands -- May 28, 2008-- DapTechnology, a world-leading supplier of advanced IEEE 1394 technology solutions to the aerospace, defense, industrial, automotive and consumer ...